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target specification (33 pages incl. this page) 03.05.99 sda 4335 version v1 pll frequency synthesizer, if counter, 7 bit adc, 7 & 4 bit dac ics for carradio applications
edition 03.99 published by infineon technologies ag i. gr., sc, balanstra?e 73, 81541 mnchen ? infineon technologies ag i.gr. 21.5.99. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for application s, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. due to technical requirements components may contain dangerous substances. for information on the types in question please cont act your nearest infineon technologies office. infineon technologies ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreeme nt we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for an y costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the infineon technologies ag, may only be used in life-support devices or systems 2 with the express written approval of the infineon technologies ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sust ain human life. if they fail, it is reasonable to assume that the health of the user may be endangered. edition 03.99 published by infineon technologies ag i. gr., sc, balanstra?e 73, 81541 mnchen ? infineon technologies ag i. gr. 21.5.99. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for application s, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. due to technical requirements components may contain dangerous substances. for information on the types in question please cont act your nearest infineon technologies office. infineon technologies ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreeme nt we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for an y costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the infineon technologies ag, may only be used in life-support devices or systems 2 with the express written approval of the infineon technologies ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sust ain human life. if they fail, it is reasonable to assume that the health of the user may be endangered. abm ? , aop ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, digitape ? , epic ? -1, epic ? -s, elic ? , falc ? 54, falc ? 56, falc ? -e1, falc ? -lh, idec ? , iom ? , iom ? -1, iom ? -2, ipat ? -2, isac ? -p, isac ? -s, isac ? -s te, isac ? -p te, itac ? , iwe ? , musac ? -a, octat ? -p, quat ? -s, sicat ? , sicofi ? , sicofi ? -2, sicofi ? -4, sicofi ? -4c, slicofi ? are registered trademarks of infineon technologies ag. ace ? , asm ? , asp ? , potswire ? , quadfalc ? , scout ? are trademarks of infineon technologies ag. ?
6'$ 5hylvlrq+lvwru\ &xuuhqw9huvlrq previous version: old page new page subjects (major changes since last revision)
table of contents page sda 4335 semiconductor group 4 21.5.99 2yhuylhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 &lufxlw'hvfulswlrq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 internal input/output circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 %orfngldjudp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 &lufxlw'hvfulswlrq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 7 bit a/d converter for adc_in1 and adc_in2 detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 if counter for sts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 output / input ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 soccar bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.6 pll synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 )xqfwlrqdo%orfn'ldjudp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3kdvhghwhfwrurxwsxwv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1.1 bus data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1.2 i2c bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 (ohfwulfdo&kdudfwhulvwlfv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.3 ac/dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3dfndjh2xwolqhv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
376623 semiconductor group 5 17.2.99 3//)uhtxhqf\6\qwkhvl]hu,)&rxqwhuelw$'& elw'$& 6'$ 9huvlrq9 %&$ 7\sh 2ughulqj&rgh 3dfndjh sda 4335 p-tssop-28 2yhuylhz the sda 4335 is a car-radio pll frequency synthesizer implemented in infineon bicmos technology b6ca. the device contains the pll, 2 pin 61.5mhz oscillator internally coupled to pll, an if counter for am & fm an 7 bit adc, an 7 & 4 bit dac and additonal 2 ports for input- or output-functions. primary applications are in car-radio systems. )hdwxuhv ? operation range 8 to 11 v ?i 2 c bus and 3wire bus operation selectable ? bus interface with low threshold voltage schmitt-trigger inputs for interfacing 3v or 5v microprocessors ? 16 bit fully programmable r- and n-counter ? resolution e.g.100khz, 50khz, 25khz, 12.5khz, 10khz, 6.25khz, 6khz, 5khz, 3khz, 1khz. ? 4 programmable phase detector currents : 0.5ma, 1ma, 2ma, 4ma. ? rail to rail loop-amplifier ? 2 chargepump-outputs for different timeconstants ? high running 2 pin crystal oscillator f q = 61.5mhz , adjustable via bus ? switchable output for 10.25mhz (500mvss @ load-capacitance 10pf) ? multiplexed 7 bit adc for adc_in1 and adc_in2. result read out via bus (2 bytes). ? 7 bit dac-output, range 0...vrefd5v ? 4 bit dac-output, range 0...vrefd5v ? 3 free programmable output ports ? port 1: free programmable output ? port 2: for am seek mode or input port for stereo-indicator ? port 3: ifc_sd for if counter resolution or input port for station-detect ? search tuning stop with if counter measurement, result read out via bus or port. fm-mode am-mode gatetime 320us...40.96ms 1ms...64ms center-frequency (standard) (double) 10.40 mhz ... 11.19375 mhz or 20.80 mhz ... 22.3875 mhz 440khz...471khz window-resolution (standard) (double) +/- 6.25 khz...100 khz +/- 12.5 khz...200 khz +/- 250hz...4khz
specification sda 4335 semiconductor group 6 21.5.99 &lufxlw'hvfulswlrq 3lq&rqiljxudwlrq port_4bit port_7bit vco vcc1 gnda pd_1 pd_0 pda nc nc port1 xtal_div6 port2_stereo quartz2 ifc_sd if_am if_fm adc_in1 adc_in2 vcc bus_mode scl sda bus_ena vrefd5v vrefd3v gndd quartz1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 sda 4335
specification sda 4335 semiconductor group 7 21.5.99 3lq'hilqlwlrqvdqg)xqfwlrqv pin no. symbol function 1ifc_sd port if_counter result output or station-detect input set by bus 2if_am if_am frequency input with counter request 3if_fm if_fm frequency input with counter request 4 adc_in1 port adc1 input 45 adc_in2 port adc2 input 6vcc positive supply voltage (8...11v) 7 bus_mode data bus input: bus-mode select must be low for i 2 c-bus-mode, must be high for 3 wire -bus-mode 8scl data bus input: clock clock input of the serial control interface with schmitt-trigger input stage 9sda data bus input / output: bidirectional data-input/output data input of the serial control interface with schmitt-trigger input stage in write-mode. data output in read-mode. 10 bus_ena bus input: enable enable input of the serial control interface with schmitt-trigger input stage. when en=h the input signals clk and da are disabled. when en=l the serial control interface is enabled. the received data are transferred to the registers with the positive edge of the en_q-signal. 11 vrefd5v reference voltage for analogue bicmos circuity 12 vrefd3v reference voltage for digital cmos circuity 13 gndd digital ground for cmos circuity 14 quartz1 reference oscillator input1 / crystal 15 quartz2 reference oscillator input2 / crystal 16 port2_stereo port2 open-drain output or stereo detection input set by bus 17 xtal_div6 output crystal frequency divided by 6 18 port1 port1 free programmable open-drain output 19 nc not connected (replaced by digtal alignment sda 4336) 20 nc not connected (replaced by digtal alignment sda 4336) 21 pda phase detector output analogue (tuningvoltage) 22 pd_0 charge pump output phase detector tristate charge pump output for pd_select=low 23 pd_1 charge pump output phase detector tristate charge pump output for pd_select=high 24 gnda analoge ground for bipolar circuity 25 vcc1 25:positive supply voltage for loop-amplifier of pll (8...11v) 26 vco vco frequency input. vco input with sensitive preampifier for pll 27 port_7bit output port 7 bit dac (range: 0... vrefd 5v) 28 port_4bit output port 4 bit dac (range: 0... vrefd 5v)
specification sda 4335 semiconductor group 8 21.5.99 ,qwhuqdolqsxwrxwsxwflufxlwv pin no. symbol function 1ifc_sd 1: if_counter output if center or station-detect input 2if_am 2: if_am input 3if_fm 3: if_fm input 4 5 adc_in1 adc_in2 4: adc input_in1 5: adc input_in2 6vcc 6: positive supply voltage for serial bus and synthesizer +5v gndd 1 gndd + 5v 2 330 135k gndd + 5v 3 330 50k 5 pf gndd +5v +5v 4 5
specification sda 4335 semiconductor group 9 21.5.99 7 bus_mode 7: bus mode input 8scl 8: bus clock input 9sda 9: data bus input / output 10 bus_ena 10: bus enable input 11 vrefd5v 11: reference voltage digital section 5v 12 vrefd3v 12: reference voltage for digital section 3v 13 gndd 13: ground for serial bus and synthesizer pin no. symbol function +5v gndd + 5v 7 330 +5v gndd + 5v 8 330 gndd + 5v 9 330 +5v gndd + 5v 10 330
specification sda 4335 semiconductor group 10 21.5.99 14 15 quartz1 quartz2 14: reference oscillator input / crystal 15: reference oscillator input / crystal 16 port2_ster eo 16: port2 open-drain output or stereo detection input set by bus 17 xtal_di v6 17: crystal oscillator auxiliary output (10.25 mhz) 18 port1 18: switch port output 2 (open drain) 19 nc not connected 20 nc not connected pin no. symbol function 2,5 k 5k 5k 14 15 + v v+ 3v gndd 2k 200ff 17 + 5 v gndd 18 330
specification sda 4335 semiconductor group 11 21.5.99 21 pda 21: pll phase detector output analog (tuning voltage) 22 23 pd_0 pd_1 22: pll charge pump output (phase detector tristate charge pump output) 23: pll charge pump output (phase detector tristate charge pump output) 24 gnda 24: ground for loop amplifier 25 vcc1 25: positive power supply for loop-amplifier 26 vco 26: vco input pin no. symbol function gndd pd vccd +5 v 21 3k 12 i pda pd +5 v +5 v +5 v 22 23 gndd + 5v 26 330 15p 10k 10k
specification sda 4335 semiconductor group 12 21.5.99 27 port_7bit 27: output port 7 bit 28 port_4bit 28: output port 4 bit pin no. symbol function gndd vcc 27 10k 2.5k gndd vcc 28 10k 2.5k
specification sda 4335 semiconductor group 13 21.5.99 %orfngldjudp port_4bit port_7bit vco vcc1 gnda pd_1 pd_0 pda nc nc port1 xtal_div6 port2_stereo quartz2 ifc_sd if_am if_fm adc_in1 adc_in2 vcc bus_mode scl sda bus_ena vrefd5v vrefd3v gndd quartz1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 if- counter dac 4, dac 7 2 channel adc pll i 2 c- 3w bus ports v ref crystal oscillator
specification sda 4335 semiconductor group 14 21.5.99 &lufxlw'hvfulswlrq the sda 4335 is a fm car radio pll synthesizer system with if counter for sts, a 2 channel multi- plexed 7 bit adc, a 7 bit dac- and a 4 bit dac multifunctional output. the serial bus is switchable between i 2 c and 3 wire bus mode. elw$'frqyhuwhuiru$'&b,1dqg$'&b,1ghwhfwru the 7 bit a/d converter has two input channels and works as successive approximation converter. the conversion time for both input signals is t = 32 m s. the 7-bit digital-words from both channels (14 bit) are read out together via bus into two bytes with the read subadress 82h. the input voltage range for both channels is 0...vrefd5v. ,)frxqwhuiru676 for fm-mode the center frequency is adjustable in 128 steps (6.25khz for standard if-frequency/ 12.5khz for double if-frequency) from 10.40mhz...11.19375mhz (standard) / 20.80mhz ... 22.3875mhz (double). the gate-time is adjustable in 8 steps from 320us...40.96ms and the tolerance of the accepted count value, the window is adjustable in 5 steps from +/- (250hz...4khz). for am-mode the center frequency is adjustable in 128 steps (1khz) from 384khz ... 511khz. mode is selectable by bus. in fm-mode the input if_am is going low with a internally nmos open drain transistor. in am-mode the input if_fm is going low with a internally nmos opendrain transistor. the gate-time is adjustable in 7 steps from 1ms...64ms and the tolerance of the accepted count value, the window is adjustable in 5 steps from +/- (250hz...4khz). the results if_cent and if_window are read out via bus (read-subadress 82h). the result if_cent is optional avialable on pin ifc_sd set by bus. if the if frequency into the preselected window, if_cent goes from high to lo level. the if frequency is outside the preselected window, if_cent is high. the bit if_window is a hint if-frequency is to low (if_window=high) or is to high (if_window=low). in addition to the frequency measurement, thresholds for adc_in1 and adc_in2 voltages can be programmed via bus (subaddress 0bh). if_cent will only go to low level in case fo adc_in1 and adc_in2 voltages are beyond the thresholds and the frequency is inside the window. when setting the thresholds to zero adc_in1 and adc_in2 evaluation is disabled. &u\vwdorvfloodwru a master crystal oscillator provides all necessary clock frequencies for the whole ic. a 61.5 mhz crystal is used in 3rd harmonic mode. the oscillator frequency can fine tuned with a serial bus controlled 4 bit d/a converter. the crystal frequency is used as reference frequency for the pll oscillator and if counter. it is also used as clock for the adc. finally the crystal frequency divided by 6 (10.25 mhz) is available at a pin as low pass filtered voltage. it can be disabled with the serial bus. 2xwsxwlqsxw3ruwv port1 is a nmos open drain output, port2_stereo and ifc_sd are nmos open drain outputs in port mode or inputs set by bus. port_7bit / port_4bit are multifunctionaly dac outputs with a output voltage range from v out = 0...vrefd5v, with a resolution from 7 bit and 4 bit. 62&&$5%xv the sda 4335 supports the i 2 c bus protocol (2 wire) or 3 wire bus protocol operation selectable by pin 7: bus_mode (i 2 c=low, 3w=high). all bus pins ( bus_mode, scl, sda, bus_ena) are schmitt-triggered input buffer for 3v or 5v m c. the bit stream begins with the most significant bit (msb), is shifted in (write mode) on the low to high transition of clk and is shifted out (read mode) on the high to low transition of clk.
specification sda 4335 semiconductor group 15 21.5.99 i 2 c bus mode in this mode pin7 (bus_mode) = low and pin10 (bus_ena)=low. in this mode sda is a bidirectional input / output pin. data transition: data transition on the pin sda must only occur when the clock scl is low. sda transitions while scl is high will be interpreted as start or stop condition. start condition (sta): a start condition is defined by a high to low transition of the sda line while scl is at a stable high level.this start condition must precede any command and initiate a data transfer onto the bus. stop condition (sto): a stop condition is defined by a low to high transition of the sda while the scl line is at a stable high level. this condition terminate the communication between the devices and forces the bus interface into the initial conditions. acknowlage (ack): indicates a successful data transfer. the transmitter will release the bus after sending 8 bit of data. during the 9th clock cycle the receiver will pull the sda line to low level to indicate it has receive the 8 bits of data correctly. data transfer write mode: to start the communication, the bus master must initiate a start condition, followed by the 8bit chip address (write). the chip address for the sda 4335 is fixed as 1100110 (msb at first). the last bit (lsb=a0) of the chip address byte defines the typ of operation to be performed: a0=1, a read operation is selected and a0=0, a write operation is selected. after this comparision the sda 4335 will generate an ack. after this device addressing the desired sub address byte and data bytes must be followed. the subaddresses determines which one of the 9 data bytes (00h...07h, 0bh) is transmitted first. at the end of data transition the master must be generate the stop condition. data transfer read mode: to start the communication in the read mode, the bus master must initiate a start condition, fol lowed by the 8bit chip address (write: a0=0), followed by the sub address read (82h or 83h), followed by the chip address (read: a0=1). after that procedure the 16bit data register 82h or the 8bit data register 83h is read out. after the first 8 bit read out, the up mandatory send low during the ack-clock. after the second 8 bit read out the up mandatory send high during the ack-clock. at the end of data transition the master must be generate the stop condition. 3w bus mode in this mode pin4 (bus_mode) =high. pin6 (sda) is a bidirectional input / output pin in this mode. pin8 (bus_ena) is used to activate the bus interface to allow the transfer of data to / from the device. when bus_ena is in an inactive high state, shifting is inhibited. data transition: data transition on the pin sda must only occur when the clock scl is low. to transfer data to / from the device, bus_ena (which must start inactive high) is taken low, a serial transfer is made via sda, clk and bus_ena is taken back high. the bit stream needs neither the chip address. data transfer write mode: to start the communication, the bus_ena is taken low. the desired sub address byte and data bytes must be followed. the subaddresses determines which one of the 9 data bytes (00h...07h, 0bh) is transmitted first. at the end of data transition the bus_ena must be high. data transfer read mode: to start the communication in the read mode, the bus_ena is taken low, followed by the sub address read (82h or 83h). after that the device is ready to read out the 16bit data register 82h or the 8bit data register 83h. at the end of data transition the bus_ena must be high.
specification sda 4335 semiconductor group 16 21.5.99 3//6\qwkhvl]hu r / n counter the sda 4335 has 2 identical 16bit counter for r and n path. input frequency for the r-counter is the buffered xtal-frequency (61.5mhz). tuning steps can be selected by the 16bit r-counter from f r = 6.25khz...100khz. input frequency for the n-counter is the buffered lo-frequency (in fm mode 98.2mhz...118.7mhz). three state phase comparator the phase comparator generates a phase error signal according to phase difference between f r (r counter output) and f n (n counter output).this phase error signal drives the charge pump current generator. polarity is fixed positiv for this application note. charge pump the charge pump generates signed pulses of current. 4 current values and 2 outputs are available. loop amp the integrated rail to rail loop amplifier allows an active loop filter design with external components. two modes are availiable with status bit d11: high speed and normal mode.
specification sda 4335 semiconductor group 17 21.5.99 )xqfwlrqdo%orfn'ldjudp vco xtal_in xtal_in_q gnd_a if_fm if_am vcc gnd vref_5 vref_3 bus_move scl sda en_q adc_in2 adc_in1 mux i 2 c-bus or 3 wire-bus supply voltage ref osc 16 bit n- counter 16 bit r- counter mux 4 bit dac 7 bit dac phase comp charge pump sample and hold 7 bit adc div by 123 div by 6 22 bit-ref- counter 19 bit-gate- counter if-count result control port extension output or input switch lp1/lp2 - pd_1 pd_0 vcc1 pda xtal_div6 port_4bit port_7bit port1 port2_stereo ifc_sd bus bus
specification sda 4335 semiconductor group 18 21.5.99 3kdvhghwhfwrurxwsxwv pd_0/1 f r f n p-channel tri-state. polarity pos. frequency f v > f r or f v leading frequency f v = f r frequency f v < f r or f v lagging n-channel
specification sda 4335 semiconductor group 19 21.5.99 bus interface pin function %xv'dwd)rupdw i 2 c bus write mode i 2 c bus read mode 1): mandatory low send by up, 2): mandatory high send by up 3w bus write mode 3w bus read mode chipaddress organisation subaddress pin name bus_mode bus_ena scl sda function bus mode select enable serial clock serial data i2c-mode low high=inactiv, low=activ clock input data in / out 3wire mode high msb chip address (write) lsb msb sub address (write) 00h...07h, 0bh lsb msb data in x...0 (x=7 or 15) lsb sta 11001100 ack s7 s6 s5 s4 s3 s2 s1 s0 ack dx ... d5 d4 d3 d2 d1 d0 ack sto msb chip address (write) lsb msb sub address (read) 82h / 83h lsb msb chip address (read) lsb sta 11001100 ack 10000010 ack sta 11001101 ack msb data out from sub add 82h lsb msb data out from sub add 82h lsb r15 r14 r13 r12 r11 r10 r9 r8 ack 1) r7 r6 r5 r4 r3 r2 r1 r0 ack 2) sto msb data out from sub add 83h lsb r7 r6 r5 r4 r3 r2 r1 r0 ack 2) sto msb sub address (write) 00h...07h, 0bh lsb msb data in x...0 (x=7 or 15) lsb s7 s6 s5 s4 s3 s2 s1 s0 dx ... d5 d4 d3 d2 d1 d0 msb sub address (read) 82h lsb msb data out from sub add 82h (msb) lsb msb data out from sub add 82h (lsb) lsb 10000010 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 msb sub address (read) 83h lsb msb data out from sub add 83h (msb) lsb 1 0 0 0 0 0 1 1 r7 r6 r5 r4 r3 r2 r1 r0 chip address (only i 2 c mode) msb lsb function 11001100chip address write 11001101chip address read sub addresses of data registers write msb bin lsb hex function 0000000000hstatus 00000001 01h r_counter 00000010 02h n_counter 00000011 03h dac7 00000100 04h if_count_p1 00000101 05h if_count_p2 00000110 06h specials 00000111 07h dac4 00001011 0bh comp_preset
specification sda 4335 semiconductor group 20 21.5.99 data byte specification sub address of data register read msb bin lsb hex function 1000001082h result adc_in2, adc_in1, if_window and if_center 1000001183hresult_misc status subaddress 00h r_counter subaddress 01h n_counter subaddress 02h comp_preset subaddress 0bh bit function bit function bit function bit function msb d15 not used (must be=0) msb d15 2 15 msb d15 2 15 msb d15 not used d14 port2_stereo d14 2 14 d14 2 14 d14 v_in1_2 6 d13 port1 d13 2 13 d13 2 13 d13 v_in1_2 5 d12 stereo-flag d12 2 12 d12 2 12 d12 v_in1_2 4 d11 loopamp current d11 2 11 d11 2 11 d11 v_in1_2 3 d10 not used (must be=0) d10 2 10 d10 2 10 d10 v_in1_2 2 d9 not used (must be=0) d9 2 9 d9 2 9 d9 v_in1_2 1 d8 am / fm d8 2 8 d8 2 8 d8 v_in1_2 0 d7 adc_single d7 2 7 d7 2 7 d7 not used d6 adc_mode d6 2 6 d6 2 6 d6 v_in2_2 6 d5 adc_on d5 2 5 d5 2 5 d5 v_in2_2 5 d4 dac4 d4 2 4 d4 2 4 d4 v_in2_2 4 d3 pd_select d3 2 3 d3 2 3 d3 v_in2_2 3 d2 cp_current 2 d2 2 2 d2 2 2 d2 v_in2_2 2 d1 cp_current 1 d1 2 1 d1 2 1 d1 v_in2_2 1 d0 lsb cp_mode d0 lsb 2 0 d0 lsb 2 0 d0 lsb v_in2_2 0 dac7 subaddress 03h if_count_p1 subaddress 04h if_count_p2 subaddress 05h specials subaddress 06h if_dac4 subaddress 07h bit function bit function bit function bit function bit function msb d7 enable msb d7 enable msb d7 cf_mode msb d7 xtal_div6 msb d7 not used d6 dac7_6 d6 station_ detect d6 cf_6 d6 not used d6 not used d5 dac7_5 d5 win_2 d5 cf_5 d5 not used d5 not used d4 dac7_4 d4 win_1 d4 cf_4 d4 not used d4 not used d3 dac7_3 d3 win_0 d3 cf_3 d3 xtal_3 d3 dac4_3 d2 dac7_2 d2 gate_2 d2 cf_2 d2 xtal_2 d2 dac4_2 d1 dac7_1 d1 gate_1 d1 cf_1 d1 xtal_1 d1 dac4_1 d0 lsb dac7_0 d0 lsb gate_0 d0 lsb cf_0 d0 lsb xtal_0 d0 lsb dac4_0
specification sda 4335 semiconductor group 21 21.5.99 results adc_in1, adc_in2 and if counter subaddress 82h (read address) result misc subaddress 83h bit function bit function msb d15 if_window msb d7 if_window d14 adc_in2_2 6 d6 if_center d13 adc_in2_2 5 d5 adc_in1_comp d12 adc_in2_2 4 d4 adc_in2_comp d11 adc_in2_2 3 d3 res d10 adc_in2_2 2 d2 res d9 adc_in2_2 1 d1 station_detect d8 adc_in2_2 0 d0 lsb stereo_flag d7 if_center d6 adc_in1_2 6 d5 adc_in1_2 5 d4 adc_in1_2 4 d3 adc_in1_2 3 d2 adc_in1_2 2 d1 adc_in1_2 1 d0 lsb adc_in1_2 0 status, subaddress 00h msb lsb msb lsb function d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 these bits must be = 0 01 0 opendrain port2_stereo output = high level (port-mode) 00 0 opendrain port2_stereo output = low level (port-mode) 0x 1 opendrain port2_stereo is input for stereoflag 01 opendrain port1 output = high level 00 opendrain port1 output = low level 01 loopamp currentsource high (i loopamp =2.4ma) for high speed tuning 0 0 loopamp currentsource low (i loopamp =1.2ma) 0 1 am-mode 00 fm-mode 0 0 0 1 7 bit ad converter enabled for single mode, stop 0101 7 bit ad converter enabled for single mode start. to restart single mode write the same bits once more. 0 0 1 1 7 bit ad converter enabled for continuos mode run. 0 x x 1 7 bit ad converter enabled for single or continous mode 0xx0 7 bit ad converter disabled for single and continous mode 0 1 dac4 enabled (see subaddress 07h) 0 0 dac4 disabled (see subaddress 07h) 0 1 phase detector select; pd_1=on, pd_0=off 0 0 phase detector select; pd_1=off, pd_0=on 0 1 1 chargepump current i cp3 = 4ma 0 1 0 chargepump current i cp2 = 2ma
specification sda 4335 semiconductor group 22 21.5.99 0 0 1 chargepump current i cp1 = 1ma 0 0 0 chargepump current i cp0 = 500ua 0 1 chargepump enabled 0 0 chargepump disabled subaddress 01h, r_counter and subaddress 02h, n_counter msb lsb msb lsb function d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 1 1 11 1 1111111 divider by 65535 0 0 0 0 0 1 11 1 1010000 divider by 2000 0 0 0 0 0 1 00 1 1001110 divider by 1230 0 0 0 0 0 0 11 1 1101000 divider by 1000 0 0 0 0 0 0 10 0 1100111 divider by 615 0 0 0 0 0 0 00 0 1100100 divider by 100 0 0 0 0 0 0 00 0 0001010 divider by 10 0 0 0 0 0 0 00 0 0000010 divider by 2
specification sda 4335 semiconductor group 23 21.5.99 * valid for d7=0 in subaddress 05h in fm_mode multiply window value with 2 for d7=1 in subaddress 05h (e. g. d7=0 window= 6.25 khz d7=1 window= 12.5 khz) subaddress 03h, dac7 subaddress 04h, if_count_p1 msb lsb function msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 dac7 enabled 1 if_count enabled 0 xxxxxxx dac7 disabled 0 if_count disabled 1 1111111 dac7_127 (full scale) 1 port ifc_sd is input for station_detect to start if_count externally, if the station detetect goes to high 0 port ifc_sd is output for result if_center fm_mode / am_mode 1 1000011 dac7_66 (msb+3*lsb) 100 window= 100khz* / 4khz 1 1000010 dac7_65 (msb+2*lsb) 011 window= 50khz* / 2khz 1 1000001 dac7_64 (msb+lsb) 010 window= 25khz* / 1khz 1 1000000 dac7_63 (msb) 001 window= 12.5khz* / 500hz 1 0111111 dac7_62 (msb-lsb) 000 window= 6.25khz* / 250hz 1 0111110 dac7_61 (msb- 2*lsb) 1 1 1 gatetime= 40.96ms/not used 1 0111101 dac7_60 (msb- 3*lsb) 1 1 0 gatetime= 20.48ms / 64ms 1 0111100 dac7_59 (msb- 4*lsb) 1 0 1 gatetime= 10.24ms / 32ms 1 0 0 gatetime= 5.12ms / 16ms 0 1 1 gatetime= 2.56ms / 8ms 1 0000010 dac7_2 (zero+2*lsb) 0 1 0 gatetime= 1.28ms / 4ms 1 0000001 dac7_1 (zero+lsb; lsb=39mv) 0 0 1 gatetime= 640us / 2ms 1 0000000 dac7_0 zero 000 gatetime= 320us / 1ms
specification sda 4335 semiconductor group 24 21.5.99 subaddress 05h, if_count_p2, fm_mode centerfrequency = cf, cf_fm step = 6.25khz/12.5khz subaddress 05h, if_count_p2, am_mode centerfrequency = cf, cf_am step = 1khz) msb lsb function msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 centerfrequency cf1 0 centerfrequency cfo 0 centerfrequency cf0 0 1010111 cf_am= 471khz 1 1111111 cf1= 22.3875 mhz 0 1010110 cf_am= 470khz 0 1111111 cf0= 11.1937 mhz 0 1010101 cf_am= 469khz 0 1010100 cf_am= 468khz 1 1000000 cf1= 22.600 mhz 0 1010011 cf_am= 467khz 0 1000000 cf0= 10.800 mhz 0 1010010 cf_am= 466khz 0 1010001 cf_am= 465khz 1 0110001 cf1= 21.4125 mhz 0 1010000 cf_am= 464khz 0 0110001 cf0= 10.70625 mhz 0 1001111 cf_am= 463khz 1 0110000 cf1= 21.400 mhz 0 1001110 cf_am= 462khz 0 0110000 cf0= 10.700 mhz 0 1001101 cf_am= 461khz 1 0101111 cf1= 21.3875 mhz 0 1001100 cf_am= 460khz 0 0101111 cf0= 10.69375 mhz 0 1001011 cf_am= 459khz 0 1001010 cf_am= 458khz 1 0100000 cf1= 21.200 mhz 0 1001001 cf_am= 457khz 0 0100000 cf0= 10.600 mhz 0 1001000 cf_am= 456khz 0 1000111 cf_am= 455khz 1 0010000 cf1= 21.000 mhz 0 1000110 cf_am= 454khz 0 0010000 cf0= 10.500 mhz 0 1000101 cf_am= 453khz 0 1000100 cf_am= 452khz 1 0000000 cf1= 20.800 mhz 0 1000011 cf_am= 451khz 0 0000000 cf0= 10.400 mhz 0 1000010 cf_am= 450khz 0 1000001 cf_am= 449khz centerfrequencies fm for 0 1000000 cf_am= 448khz d7=1 cf1= 20.800 mhz +n*12.5 khz, cf step =12.5 khz 0 0111111 cf_am= 447khz d7=0 cf0= 10.400 mhz +n*6.25 khz, cf step =6.25 khz 0 0111110 cf_am= 446khz n=0...127 0 0111101 cf_am= 445khz 0 0111100 cf_am= 444khz 0 0111011 cf_am= 443khz 0 0111010 cf_am= 442khz 0 0111001 cf_am= 441khz 0 0111000 cf_am= 440khz centerfrequencies am for d7=0 cf_am=384khz+n*1khz, cf step =1khz n=0...127
specification sda 4335 semiconductor group 25 21.5.99 subaddress 06h, specials subaddress 07h, if_dac4 msb lsb function msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 x x x not used x x x x not used 1 xtal_div6 enabled 1111 dac4_15 (full scale) 0 xtal_div6 disabled 1110 dac4_14 1 1 1 1 xtal_adjust c l = 15 pf 1101 dac4_13 1 1 1 0 xtal_adjust c l = 14pf 1100 dac4_12 1 1 0 1 xtal_adjust c l = 13 pf 1011 dac4_11 1 1 0 0 xtal_adjust c l = 12 pf 1010 dac4_10 (msb+2*lsb) 1 0 1 1 xtal_adjust c l = 11 pf 1001 dac4_9 (msb+lsb) 1 0 1 0 xtal_adjust c l = 10 pf 1000 dac4_8 (msb) 1 0 0 1 xtal_adjust c l = 9 pf 0111 dac4_7 1 0 0 0 xtal_adjust c l = 8 pf 0110 dac4_6 0 1 1 1 xtal_adjust c l = 7 pf 0101 dac4_5 0 1 1 0 xtal_adjust c l = 6 pf 0100 dac4_4 0 1 0 1 xtal_adjust c l = 5 pf 0011 dac4_3 (zero+3*lsb) 0 1 0 0 xtal_adjust c l = 4 pf 0010 dac4_2 (zero+2*lsb) 0 0 1 1 xtal_adjust c l = 3 pf 0001 dac4_1 (zero+lsb; lsb=333mv) 0 0 1 0 xtal_adjust c l = 2 pf 0000 dac4_0 zero 0 0 0 1 xtal_adjust c l = 1pf 0 0 0 0 xtal_adjust c l = 0pf subaddress 0bh, comp preset msb lsb msb lsb function d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x not used in1p2 6 in1p2 5 in1p2 4 in1p2 3 in1p2 2 in1p2 1 in1p2 0 preset value in1 in2p2 6 in2p2 5 in2p2 4 in2p2 3 in2p2 2 in2p2 1 in2p2 0 preset value in2 subaddress 82h, read results from adc_in1, adc_in2 and if counter msb lsb msb lsb function d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 11 if_counter result: if frequency is outside the desired window. if frequency is lower as the desired if frequency. 01 if_counter result: if frequency is outside the desired window.if frequency is higher as the desired if frequency. x0 if_counter result: if frequency is inside the desired window in2 _2 6 in2 _2 5 in2 _2 4 in2 _2 3 in2 _2 2 in2 _2 1 in2 _2 0 result adc_in2 byte in2_6...in2_0 in1 _2 6 in1 _2 5 in1 _2 4 in1 _2 3 in1 _2 2 in1 _2 1 in1 _2 0 result adc_in1 byte in1_6...in1_0
specification sda 4335 semiconductor group 26 21.5.99 subaddress 83h, read results from misc msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 11 if_counter result: if frequency is outside the desired window. if frequency is lower as the desired if frequency. 01 if_counter result: if frequency is outside the desired window. if frequency is higher as the desired if frequency. x0 if_counter result: if frequency is inside the desired window. 1 in1_voltage is higher than the preseted value (d8 .. d14) in 0bh 0 in1_voltage is lower than the preseted value (d8 .. d14) in 0bh 1 in2_voltage is higher than the preseted value (d0 .. d6) in 0bh 0 in2_voltage is lower than the preseted value (d0 .. d6) in 0bh 11 not used 1 start if_counter on the rising edge from low to high see also d7 & d6 in subadress 04h, if_count_p1 0 standby if_counter x input signal stereo_flag from port2_stereo (x=0 or 1)
specification sda 4335 semiconductor group 27 21.5.99 , &%xv7lplqj 3w-bus timing scl sda bus_ena t buf s p t hd.dat t hd.sta t high t f t low t r t su.dat t hd.sta t sp p t su.sto s t su.sta t su.enasda pulsed or mandatory low bus_mode = low t su.enasda t su.enasda t high scl sda bus_ena s t hd.dat t hd.sta t high t f t low t r t su.dat t sp p t su.sto t su.staena bus_mode = high t su.stoena t when
specification sda 4335 semiconductor group 28 21.5.99 1) only in i 2 c bus mode 2) only in 3w bus mode 3) c b = capacitance of one bus line in pf. note that the maximum t f for the sda and scl bus lines quoted at 300ns is longer than the specified maxi- mum t of for the output stages (250ns).this allows series protection resistors to be connected between the sda / scl pins and the sda /scl bus lines without exceeding the maximum specified t f . parameter symbol limit values unit min. max. low level input voltage (sda, scl, bus_ena, bus_mode) v il -0.5 0.90 v high level input voltage (sda, scl, bus_ena, bus_mode) v ih 2.10 5.50 v pulse widh of spikes which must be suppressed by the input filter t sp 050ns low level output voltage 3ma sink current (sda) v ol 00.40v output fall time from v ihmin to v ilmax with a bus capaci- tance from 10pf to 400pfwith up to 3ma t of 20+0.1c b 3) 250 ns scl clock frequency f scl 0 400 khz bus free time between a stop and start condition 1) t buf 1.3 us hold time (repeated) start condition. after this period, the first clock pulse is generated. 1) t ho.sta 0.6 us low period of the scl clock t low 1.3 us high period of the scl clock t high 0.6 us set-up time for a repeated start condition 1) t su.sta 0.6 us data hold time t hd.dat 0ns data set -up time t su.dat 100 ns rise, fall time of both sda and scl signals t r , t f 20+0.1c b 3) 300 ns set-up time for stop condition 1) t su.sto 0.6 us capacitive load for each bus line c b 400 pf setup time scl to bus_ena 2) t su.sclen 0.6 us h-pulsewidth (bus_ena) t when 0.6 us
specification sda 4335 semiconductor group 29 21.5.99 (ohfwulfdo&kdudfwhulvwlfv $evroxwh0d[lpxp5dwlqjv the maximal ratings may not be exceeded under any circumstances, not even momentary and individual, as permanent damage to the ic will result. all values are referred to ground (pin), unless stated otherwise. all currents are designated according to the source and sink principle, i.e. if the device pin is to be regarded as a sink (the current flows into the stated pin to internal ground), it has a negative sign, and if it is a source (the current flows from vs across the designated pin), it has a positive sign. parameter symbol limit values units min. max. esd-protection all bipolar pins hbm ( r=1.5k w , c=100pf ) v esd - 2 2 kv esd-protection all cmos pins hbm ( r=1.5k w , c=100pf ) v esd t.b.d. t.b.d. kv total power dissipation p tot 150 mw ambient temperature t a - 40 85 c junction temperature t j 125 c storage temperature t stg - 40 125 c thermal resistance p-tssop-28 (sys-air) t thsa 114 k/w
specification sda 4335 semiconductor group 30 21.5.99 2shudwlqj5dqjh within the operational range the ic operates as described in the circuit description. the ac / dc characteristic limits are not guaranteed. $&'&&kdudfwhulvwlfv ac / dc characteristics involve the spread of values guaranteed in the specified supply voltage and ambient temperature range. typical characteristics are the median of the production. parameter symbol limit values unit test conditions min max supply voltage v vcc 811v current consumption i vcc 30 ma ambient temperature t a - 40 85 c parameter t a = 25 c,v vcc = 8.5v symbol limit values unit test conditions min typ max power supply total current consumption i vcc 20 ma crystal oscillator operating frequency f 16-17 61.5 mhz 3rd harmonic negative input impedance z 16-17 - 250 w f = 61.5 mhz negative input impedance z 16-17 1.4 k w f = 20.5 mhz input impedance crystal r cr tbd w 3rd harmonic spurious harmonics crystal a sp - 20 db f < 200 mhz bus controlled adjust range d f adj 40 ppm see diagram sub06h bus controlled output xtal_div6 v xtal_div6 _on 500 mv pp f = 10.25 mhz, c load = 10pf v xtal_div6 _on 1.5 v dc f = 10.25 mhz, c load = 10pf v xtal_div6 _off 60 db signal supression f=10.25 mhz v xtal_div6 _off 50 mv dc c load = 10pf chargepump output pd_1, pd_0 (loopfilter input) dc voltage v pd_1 v pd_0 2.5 v locked dc current i pd_1_3 i pd_0_3 3.2 4 4.8 ma see status, subaddress 00h, bit d1, d2 v pd_0/1 = 2.5v dc current i pd_1_2 i pd_0_2 1.6 2 2.4 ma dc current i pd_1_1 i pd_0_1 0.8 1 1.2 ma dc current i pd_1_0 i pd_0_0 400 500 600 ua tristate output current i pd_1_off i pd_0_off 0.1 10 na v pd_0/1 = 2.5v , guaranteed by design
specification sda 4335 semiconductor group 31 21.5.99 loop amplifier tuningvoltage output (loopfilter output) low output voltage v pda_l 0 tbd. 400 mv i tune = 100 ua high output voltage v pda_h v vcc - 0.5v tbd. v cc mv i tune = -100 ua high output current source low output current source i pda_h i pda_l -2.4 -1.2 ma v tune = 4v, v pd_1 = 0v, v pd_0 = 0v (see status, subaddress 00h, bit d11) if_counter input sensitivity am v if_1 50 tbd. mv f if_1 = 440...471khz input impedance am z if_1 180 k w f if_1 = 455khz input sensitivity fm v if_0 50 tbd. mv f if_0 = 10.60...10.80mhz input impedance fm z if_0 10 k w f if_0 = 10.70mhz pll for synthesizer ( see pll synthesizer on page 16 ) pll / vco step size (programmable via r-counter) f ref 6.25 100 khz f crystal = 61.5 mhz n-counter divide ratio n 2 65535 16-bit r-counter divide ratio r 2 65535 16-bit input sensitivity v vco 50 tbd. mv f vco = 70...120mhz input impedance z vco 2.5 k w f vco = 120mhz adc converter adc_in1 / in2 input voltage range v adc_in1/2 0 vrefd5v v tbd. sampling capacitance c s 5pf least significant bit v lsb 39, 37 mv zero offsetfailure v zero tbd. mv full scale v fs tbd. vrefd5v tbd. v nonlinearity d v+/-1.5lsb coverting time for both cannels f conv 32 us dac_7 converter port_7bit output voltage range v port_7bit 05,40v tbd. least significant bit v lsb 39.37 mv zero offsetfailure v zero tbd. mv full scale v fs tbd. vrefd5v tbd. v nonlinearity d v+/-1.5lsb output current i port_7bit 50 ua output capacitance c port_7bit 10 pf parameter t a = 25 c,v vcc = 8.5v symbol limit values unit test conditions min typ max
specification sda 4335 semiconductor group 32 21.5.99 dac_4 converter port_4bit tbd. output voltage range v port_7bit 05,40v least significant bit v lsb 333.33 mv zero offsetfailure v zero tbd. mv full scale v fs tbd. vrefd5v tbd. v nonlinearity d v+/-1.5lsb output current i port_4bit 50 ua output capacitance c port_4bit 10 pf port outputs, port1, port2_stereo, ifc_sd ( see output / input ports on page 14 ) low output voltage v p 0 100 400 mv i p = 1 ma high leackage current i p_leack 0 100 na v p = 5 v i2c / 3-wire-bus (bus_mode, scl, sda, bus_ena) ( see i2c bus timing on page 27 and bus data format on page 19 ) h-input voltage v ih 2.10 5.50 v l-input voltage v il -0.5 0.90 v hysteresis of schmitt trigger inputs (bus_mode, scl, sda, bus_ena) v hys 0.30 v input capacity c i 5pf parameter t a = 25 c,v vcc = 8.5v symbol limit values unit test conditions min typ max
specification sda 4335 semiconductor group 33 21.5.99 3dfndjh2xwolqhv 376623 (plastic package)

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